The present invention relates to compressed bitstream decoding. More specifically, the present invention relates to methods and apparatuses for the decoding of an interruptible bitstream.
Because of the advantages digital video has to offer, in the past few decades analog video technology has evolved into digital video technology. For example, digital video can be stored and distributed cheaper than analogy video because digital video can be stored on randomly accessible media such as magnetic disc drives (hard disks) and optical disc media known as compact (CDs). In addition, once stored on a randomly accessible media, digital video may be interactive, allowing it to be used in games, catalogs, training, education, and other applications.
One of the newest products to be based on digital video technology is the digital video disc, sometimes called xe2x80x9cdigital versatile discxe2x80x9d or simply xe2x80x9cDVD.xe2x80x9d These discs are the size of an audio CD, yet hold up to 17 billion bytes of data, 26 times the data on an audio CD. Moreover, DVD storage capacity (17 Gbytes) is much higher than CD-ROM (600 Mbytes) and can be delivered at a higher rate than CD-ROM. Therefore, DVD technology represents a tremendous improvement in video and audio quality over traditional systems such as televisions, VCRs and CD-ROM.
DVDs generally contain video data in compressed MPEG format. To decompress the video and audio signals, DVD players use decoding hardware to decode the incoming bitstream. FIG. 1 is a block diagram showing a prior art digital video system 100. The digital video system 100 includes a digital source 102, a digital processor 104, and a digital output 106. The digital source 104 includes DVD drives and other digital source providers, such as an Internet streaming video connection. The digital processor 104 is typically an application specific integrated circuit (ASIC), while the digital output 106 generally includes display devices such as television sets and monitors, and also audio devices such as speakers.
Referring next to prior art FIG. 2, a conventional digital processor 104 is shown. The digital processor 104 includes a decompression engine 200, a controller 202, and DRAM 204. Essentially, the bitstream is decompressed by the decompression engine 200, which utilizes the DRAM 204 and the controller 202 during the decompression process. The decompressed data is then sent to a display controller 206, which displays decompressed images on a display device, such as a television or monitor.
As stated previously, digital processors are generally embodied on ASICs. These ASICs typically map key functional operations such as variable length decoding (VLD), run-length decoding (RLD), Zig Zag Scan, inverse quantization (IQ), and inverse discrete cosine transformation (IDCT) to dedicated hardware. To gain processing speeds, techniques such as pipeline implementation of these modules are used to execute computations with available cycle time.
While an incoming bitstream is consistently supplied, such pipeline mechanisms run efficiently. However, a consistently supplied bitstream is not always possible with newer applications. For example, Internet streaming video cannot always guarantee a constant bitstream, since the connection may end or be interrupted at anytime. In addition, interruptions of the bitstream can occur in conventional DVD readers when, for example, the DVD player is not fast enough to keep pace with the rest of the system.
When the bitstream is interrupted, the conventional decompression engine 200 attempts to handle the problem by using error handling methods. However, using conventional error handling methods produces artifacts, which can be seen by users of the system. Moreover, these artifacts generally promulgate to subsequent pictures, thus making the viewing experience further displeasing for the user.
In view of the foregoing, what is needed are improved methods and apparatuses for decoding an incoming bitstream that can handle a bitstream interruption without causing artifacts. Further, the system should be robust and not add significantly to the manufacturing cost.
The present invention fills these needs by providing a decoder that halts the decoding process when bitstream data becomes unavailable. In one embodiment, the decoder includes an input register that is capable of receiving a latch command, and that is further capable of latching stored data in a particular state upon receiving the latch command. The decoder also includes decoding logic, such as variable length decoding logic, or run-length decoding logic, in communication with the input register. Further included in the decoder is an output register in communication with decoding logic, that is also capable of receiving the latch command, and that is further capable of latching stored data in a particular state upon receiving the latch command. Finally, the decoder includes a register controller in communication with both the input register and the output register. The register controller is capable of receiving a halt command from the system and, upon receiving the halt command, the register controller sends the latch command to both the input register and the output register.
In another embodiment, a method for decoding an incoming compressed bitstream is provided. The method comprises providing a halt command to a register controller that is in communication with both an input register and an output register. Next, a latch command is provided to both the input register and the output register when the register controller receives the halt command. Finally, data stored in the input register and the output register is latched when these registers receive the latch command, thereby halting operation of decoding logic which is in communication with both registers.
In yet another embodiment, an application specific integrated circuit (ASIC) for decoding an incoming compressed bitstream is disclosed. The ASIC includes a memory controller and an input register that is capable of receiving a latch command, and that is further capable of latching stored data in a particular state upon receiving the latch command. The ASIC also includes decoding logic, such as variable length decoding logic, or run-length decoding logic, in communication with the input register. Further included in the ASIC is an output register in communication with decoding logic, that is also capable of receiving the latch command, and that is further capable of latching stored data in a particular state upon receiving the latch command. Finally, the ASIC includes a register controller in communication with both the input register and the output register. The register controller is capable of receiving a halt command from the system and, upon receiving the halt command, the register controller sends the latch command to both the input register and the output register.
Advantageously, the present invention avoids or reduces artifacts generated in response to interruptions of the incoming bitstream. Unlike conventional decoders, which attempt to continuously decode regardless of whether data is available or unavailable, the present invention avoids artifacts by halting decoding operations when data becomes unavailable to the decoder.
In addition, the present invention allows for greater efficiency in decoding by providing a mechanism that allows for synchronization of memory writes by different decoding modules. By halting decoding and memory write operations when write operation conflicts occur, the present invention avoids the need of large buffers of time, used conventionally to prevent memory write conflicts.